PowerPC 750 SCM RISC Microprocessor
PID8p-750
Preliminary Copy
IEEE 1149.1 AC Timing Specifications
The table below provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 9, Figure 10,
Figure 11, and Figure 12. The five JTAG signals are; TDI, TDO, TMS, TCK, and TRST.
JTAG AC Timing Specifications (Independent of SYSCLK)
See Table “Recommended Operating Conditions1,2,3,” on page 6 for operating conditions, CL = 50pF.
Num
Characteristic
TCK frequency of operation
Min
0
Max
25
—
Unit
MHz
ns
Notes
1
2
TCK cycle time
40
15
0
TCK clock pulse width measured at 1.4V
TCK rise and fall times
—
ns
3
2
ns
4
4
spec obsolete, intentionally omitted
TRST assert time
5
25
4
—
—
—
20
19
—
—
12
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
6
Boundary-scan input data setup time
Boundary-scan input data hold time
TCK to output data valid
7
16
4
2
8
3, 5
3, 4
9
TCK to output high impedance
TMS, TDI data setup time
TMS, TDI data hold time
3
10
11
12
13
0
16
2.5
3
TCK to TDO data valid
5
4
TCK to TDO high impedance
Note:
1. TRST is an asynchronous level sensitive signal. Guaranteed by design.
2. Non-JTAG signal input timing with respect to TCK.
3. Non-JTAG signal output timing with respect to TCK.
4. Guaranteed by characterization and not tested.
5. Minimum spec guaranteed by characterization and not tested.
Figure 9 provides the JTAG clock input timing diagram.
Figure 9. JTAG Clock Input Timing Diagram
1
2
2
TCK
VM
VM
VM
3
3
Midpoint voltage (VM) is 1.4v for (2OVdd)
in 3.3v and (2OVdd/2) for all other I/O modes.
Page 20
Version 2.0
Datasheet
9/30/99
IBM [ IBM ]
