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IBM25PPC750L-EB0B400W 参数 Datasheet PDF下载

IBM25PPC750L-EB0B400W图片预览
型号: IBM25PPC750L-EB0B400W
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 400MHz, CMOS, CBGA360, 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360]
分类和应用: 时钟外围集成电路
文件页数/大小: 46 页 / 610 K
品牌: IBM [ IBM ]
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PowerPC 750 SCM RISC Microprocessor  
PID8p-750  
Preliminary Copy  
L2 Bus Input AC Specifications  
The L2 bus input interface AC timing specifications are found in the following table.  
L2 Bus Input Interface AC Timing Specifications  
See Table “Recommended Operating Conditions1,2,3,” on page 6, for operating conditions.  
Num  
29,30  
24  
Characteristic  
L2SYNC_IN rise and fall time  
Min  
Max  
1.0  
Unit  
ns  
Notes  
2,3  
1
Data and parity input setup to L2SYNC_IN; processor core at  
or below 375 MHz  
1.5  
ns  
24  
24  
24  
25  
Data and parity input setup to L2SYNC_IN; processor core at  
400 MHz  
1.4  
1.1  
1.0  
0.5  
ns  
ns  
ns  
ns  
1
1
1
1
Data and parity input setup to L2SYNC_IN; processor core at  
433, 450MHz  
Data and parity input setup to L2SYNC_IN; processor core at  
466, 500MHz  
L2SYNC_IN to data and parity input hold  
Note:  
1. All input specifications are measured from the midpoint voltage of the signal in question to the midpoint voltage of the rising edge of the input  
L2SYNC_IN. Input timings are measured at the pins (see Figure 7). Midpoint voltage (VM) is 1.4v for (2OVdd) in 3.3v and (2OVdd/2) for all other IO  
modes .  
2. Rise and fall times for the L2SYNC_IN input are measured from 0.5 to 1.5v.  
3. Guaranteed by design and characterization, and not tested.  
Figure 7 shows the L2 bus input timing diagrams for the PID8p-750.  
Figure 7. L2 Bus Input Timing Diagrams  
29  
30  
L2SYNC_IN  
VM  
24  
25  
VM  
VM  
ALL INPUTS  
VM = Midpoint voltage is 1.4v for (2OVdd) in 3.3v  
and (2OVdd/2) for all other I/O modes  
9/30/99  
Version 2.0  
Datasheet  
Page 17  
 
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