PowerPC 750 SCM RISC Microprocessor
PID8p-750
Preliminary Copy
L2 Bus Output AC Specifications
The following table provides the L2 bus output interface AC timing specifications for the PID8p-750 as
defined in Figure 8.
L2 Bus Output Interface AC Timing Specifications1
See Table “Recommended Operating Conditions1,2,3,” on page 6 for operating conditions, CL = 20pF3
Num
Characteristic
L2CR[14-15] is equivalent to:
01 10
Unit
Notes
2
11
Max
00
Min
—
Max
3.2
Min
—
Max
Min
—
Max
Min
—
5
5
26
26
26
26
L2SYNC_IN to output valid -
processor cores at or below 375 MHz
3.7
3.5
3.1
2.9
ns
ns
ns
ns
Rsv
Rsv
Rsv
Rsv
Rsv
Rsv
Rsv
Rsv
5
5
5
5
5
5
L2SYNC_IN to output valid -
processor core at 400MHz
—
—
—
3.0
2.6
2.4
—
—
—
—
—
—
—
—
—
L2SYNC_IN to output valid -
processor core at 433, 450MHz
L2SYNC_IN to output valid -
processor core at 466 and 500MHz
5
5
27
28
L2SYNC_IN to output hold
0.5
—
—
1.0
—
—
—
—
ns
ns
4,6
6
Rsv
—
Rsv
—
5
5
L2SYNC_IN to high impedance
3.5
4.0
Rsv
Rsv
Note:
1. All outputs are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint voltage of the signal in question. The output timings
are measured at the pins. Midpoint voltage (VM) is 1.4v for (2OVdd) in 3.3v and (2OVdd/2) for all other IO modes, .
2. The outputs are valid for both single-ended and differential L2CLK modes. For flow-through and pipelined reg-reg synchronous burst SRAMs,
L2CR[14-15] = 00 is recommended. For pipelined late-write synchronous burst SRAMs, L2CR[14-15] = 01 is recommended.
3. All maximum timing specifications assume CL = 20pF.
4. This measurement assumes CL= 5pF.
5. Reserved for future use.
6. Guaranteed by design and characterization, and not tested.
Page 18
Version 2.0
Datasheet
9/30/99
IBM [ IBM ]
