PowerPC 750 SCM RISC Microprocessor
PID8p-750
Preliminary Copy
L2 Clock AC Specifications
The following table provides the L2CLK output AC timing specifications as defined in Figure 6.
L2CLK Output AC Timing Specifications
See Table “Recommended Operating Conditions1,2,3,” on page 6, for operating conditions.
Num
Characteristic
Min
80
Max
250
Unit
MHz
ns
Notes
1,5
L2CLK frequency
L2CLK cycle time
L2CLK duty cycle
L2CLK jitter
22
23
4.0
12.5
50
%
2
3,6
4
ps
±150
Internal DLL-relock time
640
—
L2CLK
Note:
1. L2CLK outputs are L2CLKOUTA, L2CLKOUTB and L2SYNC_OUT pins. The L2CLK frequency to core frequency settings must be chosen such that the
resulting L2CLK frequency and core frequency do not exceed their respective maximum or minimum operating frequencies. L2CLKOUTA and
L2CLKOUTB must have equal loading.
2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
3. The total input jitter (short term and long term combined) must be under ± 150ps.
4. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to compute the actual time
duration in nanoseconds. Re-lock timing is guaranteed by design and characterization, and is not tested.
5. The L2CR [L2SL] bit should be set for L2CLK frequencies less than 110MHz.
6. Guaranteed by design and characterization, and not tested.
9/30/99
Version 2.0
Datasheet
Page 15
IBM [ IBM ]
