PowerPC 750 SCM RISC Microprocessor
PID8p-750
Preliminary Copy
Figure 2. SYSCLK Input Timing Diagram
1
2
3
4
4
CVIH
VM
(Midpoint
SYSCLK
Voltage)
CVIL
60x Bus Input AC Specifications
The following table provides the 60X bus input AC timing specifications for the PID8p-750 as defined in
Figure 3 and Figure 4. Input timing specifications for the L2 bus are provided in Section, “L2 Bus Input AC
Specifications” on page 17.
60X Bus Input Timing Specifications1
See Table “Recommended Operating Conditions1,2,3,” on page 6, for operating conditions.
Num
Characteristic
300,333, 350, 366,
375, 400, 433, 450, 466, 500 MHz
Unit
Notes
2
Minimum
2.5
Maximum
—
10a
Address/Data/Transfer Attribute Inputs Valid to SYSCLK (Input
Setup)
ns
ns
10b
10c
All Other Inputs Valid to SYSCLK (Input Setup)
2.5
8
—
—
3
Mode Select Input Setup to HRESET (DRTRY,TLBISYNC)
t
4,5,6,7
sysclk
11a
SYSCLK to Address/Data/Transfer Attribute Inputs Invalid (Input
Hold)
0.6
—
ns
2
11b
11c
SYSCLK to All Other Inputs Invalid (Input Hold)
0.6
0
—
—
ns
ns
3
HRESET to mode select input hold
(DRTRY, TLBISYNC)
4,6,7
Note:
1. Input specifications are measured from the midpoint voltage of the signal in question to the midpoint voltage of the rising edge of the input SYSCLK. Input
and output timings are measured at the pin (see Figure 3) Midpoint voltage (VM) is 1.4v for OVdd in 3.3v mode and OVDD/2 for all other I/O modes
2. Address/Data Transfer Attribute inputs are composed of the following–A[0-31], AP[0-3], TT[0-4],TBST, TSIZ[0-2], GBL, DH[0-31), DL[0-31], DP[0-7].
3. All other signal inputs are composed of the following–TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA, DBDIS, TBEN, QACK, TLBI-
SYNC.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 4).
5. tSYSCLK, is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to
compute the actual time duration (in ns) of the parameter in question.
6. These values are guaranteed by design, and are not tested.
7. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255 bus clocks after the
PLL re-lock time during the power-on reset sequence.
9/30/99
Version 2.0
Datasheet
Page 11
IBM [ IBM ]
