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IBM25PPC750GXECB5H83T 参数 Datasheet PDF下载

IBM25PPC750GXECB5H83T图片预览
型号: IBM25PPC750GXECB5H83T
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 933MHz, CMOS, CBGA292, 21 X 21 MM, 1 MM PITCH, CERAMIC, BGA-292]
分类和应用: 时钟外围集成电路
文件页数/大小: 74 页 / 1054 K
品牌: IBM [ IBM ]
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Datasheet  
IBM PowerPC 750GX RISC Microprocessor  
DD1.X  
3.3 Clock AC Specifications  
Table 3-7 provides the clock AC timing specifications as defined in Figure 3-1.  
Table 3-7. Clock AC Timing Specifications  
See Table 3-2 on page 15 for recommended operating conditions.1, 3, 6  
Figure 3-1  
Value  
Timing  
Reference  
Characteristic  
Unit  
Notes  
Min.  
500  
25  
Max.  
1000  
200  
40  
Processor frequency  
SYSCLK frequency  
SYSCLK cycle time  
SYSCLK slew rate  
MHz  
MHz  
ns  
1
2, 3  
4
5.0  
1.0  
25  
4.0  
V/ns  
%
2
SYSCLK duty cycle measured at 0.65 V  
SYSCLK cycle-to-cycle jitter  
Internal PLL relock time  
75  
150  
100  
ps  
4
5
µs  
Notes:  
1. Caution: The SYSCLK frequency and the PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)  
frequency, CPU (core) frequency, and PLL frequency do not exceed their respective maximum or minimum operating frequencies.  
Refer to the PLL_CFG[0:4] signal description in Table 5-2, 750GX Microprocessor PLL Configuration, on page 48 for valid  
PLL_CFG[0:4] settings.  
2. Slew rate for the SYSCLK inputs is measured from 0.4 to 1.0 V.  
3. Timing is guaranteed by design and characterization, and is not tested.  
4. See Section 3.4, Spread Spectrum Clock Generator, on page 19 for long-term jitter.  
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time  
required for PLL lock after a stable V and SYSCLK are reached during the power-on reset sequence. This specification also  
DD  
applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that hard reset (HRESET)  
must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.  
6. Lower voltage and frequency operation will be available based on characterization results. See the IBM PowerPC 750GX RISC  
Microprocessor Supplement for more information.  
Figure 3-1. SYSCLK Input Timing Diagram  
1
2
3
4
4
CVIH  
V
M
SYSCLK  
CVIL  
V
: 0.65 V  
M-SYSCLK  
Electrical and Thermal Characteristics  
Page 18 of 73  
750GX_ds_body.fm SA14-2765-02  
September 2, 2005  
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