DD 2.X
Preliminary
PowerPC 750FX RISC Microprocessor
5.2 PLL Power Supply Filtering
The 750FX microprocessor has two separate AV signals (A1V and A2V ) which provide power to the
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clock generation phase-locked loops.
Most designs are expected to utilize a single PLL configuration mode throughout the application. These type
of designs should use the default, A1V (PLL0) and tie the A2V (PLL1) signal to ground (AGND) through
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a 100 ohm resistor. This is shown in Figure 5-1 on page 36.
For designs planning to optimize power savings through dynamic switching between these dual PLL circuits,
it is recommended, though not required, that each AV have a separate voltage input and filter circuit.
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To ensure stability of the internal clock, the power supplied to the AV input signals should be filtered using
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a circuit similar to the one shown in Figure 5-1 on page 36. The circuit should be placed as close as possible
to the AV pin to ensure it filters out as much noise as possible.
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For descriptions of the sample PLL power supply filtering circuits, see Table 5-3.
Table 5-3. Sample PLL Power Supply Filtering Circuits
Samples of PLL Power Supply Filtering Circuits
Number of
Ferrite
Recommended
Circuit Design
Circuit Description
Filtering
Circuits
Circuit Figure
Notes
Beads
Single PLL circuit configuration that uses the A1V
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1
1
2
1
1
2
Figure 5-1 on page 36
Figure 5-2 on page 37
Figure 5-3 on page 38
Yes
Optional
Yes
and ties the A2V pin to GND.
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Single PLL circuit configuration that uses both the
A1V and the A2V pins and a single ferrite bead.
1, 2
2, 3
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Dual PLL configuration that uses a separate circuit
for the A1V pin and for the A2V the pin.
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Notes:
1. Optional configurations are supported, though not recommended.
2. This circuit design can be used with the Dual PLL feature enabled, though optimum power savings may not be realized.
For additional information, see Figure 5-3 Dual PLL Power Supply Filter Circuits on page 38.
3. This circuit design can be used with the Dual PLL feature enabled to optimize power savings.
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
5. System Design Information
Page 35 of 63
IBM [ IBM ]
