DD 2.X
Preliminary
PowerPC 750FX RISC Microprocessor
5. System Design Information
This section provides electrical and thermal design recommendations for successful application of the 750FX.
For more information, see the PowerPC FAQ, the PowerPC 750FX Errata list, any applicable PCNs, and the
other PowerPC documentation and application notes in the PowerPC Technical Library on our web site.
5.1 PLL Considerations
The 750FX design includes two PLLs (PLL0 and PLL1), allowing the processor clock frequency to dynami-
cally change between the PLL frequencies via software control. Use the bits in the HID1 register to specify:
1. The frequency range of each PLL
2. The clock multiplier for each PLL
3. External or internal control of PLL0
4. The selected PLL (which is the source of the processor clock at any given time)
For HID1 bit definitions, see the PowerPC 750 FX User’s Manual.
Note: The PLL configuration must adhere to the supported frequency range as specified in this document
and in the IBM 750FX Datasheet Supplement for DD2.X Product Revisions, for the minimum V condition.
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Voltages (V /AV ) should remain constant at all times.
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At power-on reset, the HID1 register contains zeroes for all the non-read-only bits (bits 7 to 31). This configu-
ration corresponds to the selection of PLL0 as the source of the processor clocks and selects the external
configuration and range pins to control PLL0. The external configuration and range pin values are accessible
to software using HID1 read-only bits 0-6. PLL1 is always controlled by its internal configuration and range
bits. The HID1 setting associated with hard reset corresponds to a PLL1 configuration of clock off, and selec-
tion of the medium frequency range.
HRESET must be asserted during power up long enough for the PLL(s) to lock, and for the internal hardware
to be reset. Once this timing is satisfied, HRESET can be negated. The processor now will proceed to
execute instructions, clocked by PLL0 as configured via the external pins. The processor clock frequency can
be modified from this initial setting in one of two ways. First, as with earlier designs, HRESET can be
asserted, and the external configuration pins can be set to a new value. The machine state is lost in this
process, and, as always, HRESET must be held asserted while the PLL relocks, and the internal state is
reset. Second, the introduction of another PLL provides an alternative means of changing the processor clock
frequency, which does not involve the loss of machine state nor a delay for PLL relock.
The following sequence can be used to change processor clock frequency.
Note: Assume PLL0 is currently the source for the processor clock.
1. Configure PLL1 to produce the desired clock frequency by setting HID1[PR1] and HID1[PC1] to the
appropriate values.
2. Wait for PLL1 to lock. The lock time is the same for both PLLs and is provided in the hardware specifica-
tion.
3. Set HID1[PS] to 1 to initiate the transition from PLL0 to PLL1 as the source of the processor clocks.
From the time the HID1 register is updated to select the new PLL, the transition to the new clock fre-
quency will complete within three (3) bus cycles. After the transition, the HID(PSS) bit indicates which
PLL is in use.
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
5. System Design Information
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