DD 2.X
Preliminary
PowerPC 750FX RISC Microprocessor
5.1.3 PLL Configuration
PLL-CFG (Table 5-2) must be set so that both SYSCLK and the core frequency are within the Clock AC
Timing Specifications shown in Table 3-6 on page 13. In addition, the core frequency must not exceed the
limit specified in the part number, and the system must meet the required specifications.
Table 5-2. 750FX Microprocessor PLL Configuration
PLL_CFG [0:4]
Processor to Bus Frequency Ratio (PBFR)
Binary
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
Decimal
0
OFF
OFF
1
2
2
2
PLL Bypass
PLL Bypass
3
1
4
2x
1
5
2.5x
6
3x
3.5x
4x
7
8
9
4.5x
5x
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
5.5x
6x
6.5x
7x
7.5x
8x
8.5x
9x
9.5x
10x
11x
12x
13x
14x
15x
16x
Notes:
1. The 2X- 2.5X Processor to Bus Ratios are currently not supported.
2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set
for 1:1 mode operation. This mode is intended for factory use only.
The AC timing specifications given in the document do not apply in PLL-bypass mode.
3. In Clock-off mode, no clocking occurs inside the 750FX regardless of the SYSCLK input.
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
5. System Design Information
Page 33 of 63
IBM [ IBM ]
