DD 2.X
Preliminary
PowerPC 750FX RISC Microprocessor
5.3 Decoupling Recommendations
Capacitor decoupling is required for the 750FX. Decoupling capacitors act to reduce high frequency chip
switching noise and provide localized bulk charge storage to reduce major power surge effects.
High frequency decoupling capacitors should be located as close as possible to the processor with low lead
inductance to the ground and voltage planes.
Decoupling capacitors are recommended on the back of the card, directly opposite the module. The recom-
mended placement and number of decoupling capacitors, 34 V -GND caps and 44 OV -GND caps are
DD
DD
described in Figure 5-4 Orientation and Layout of the 750FX Decoupling Capacitors. The recommended
decoupling capacitor specifications are provided in Table 5-4 Recommended Decoupling Capacitor Specifi-
cations. The placement and usage described here are guidelines for decoupling capacitors and should be
applied for system designs.
Table 5-4. Recommended Decoupling Capacitor Specifications
Item
Description
Type X5R or Y5V
10V minimum
0402 size
Decoupling capacitor specifications:
40 x 20 mils, nominally
1.0 mm x 0.5 mm 0.1 mm on both dimensions
100 nF
34 V -GND caps
Recommended minimum number of decou-
pling capacitors on the back of the card:
DD
44 OV -GND caps
DD
The decoupling capacitor electrodes are located directly opposite from their corresponding BGA pins where
possible. Also, each electrode for each decoupling capacitor needs to be connected to one or more BGA pins
(balls) with a short electrical path. Thus, through-vias adjacent to the decoupling capacitors
are recommended.
The card designer can expand on the decoupling capacitor recommendations by doing the following:
• Adding additional decoupling capacitors
If using additional decoupling capacitors, verify that these additional capacitors do not reduce the number
of card vias or cause the vias to lose proximity to each capacitor electrode.
• Adding additional through-vias or blind-vias
Card technologies are available that will reduce the inductance between the decoupling capacitor and the
BGA pin (ball). Replacing single vias with multiple vias is very effective. Place GND vias close to V or
DD
OV vias to reduce loop inductance.
DD
For more information on power layout and bypassing, see the IBM Application Note, “PowerPC 750FX Layout
and Bypassing.
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
5. System Design Information
Page 39 of 63
IBM [ IBM ]
