DD 2.X
PowerPC 750FX RISC Microprocessor
Preliminary
Table 5-2. 750FX Microprocessor PLL Configuration (Continued)
PLL_CFG [0:4]
Processor to Bus Frequency Ratio (PBFR)
Binary
11011
11100
11101
11110
11111
Decimal
27
17x
18x
19x
20x
28
29
30
3
31
Off
Notes:
1. The 2X- 2.5X Processor to Bus Ratios are currently not supported.
2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set
for 1:1 mode operation. This mode is intended for factory use only.
The AC timing specifications given in the document do not apply in PLL-bypass mode.
3. In Clock-off mode, no clocking occurs inside the 750FX regardless of the SYSCLK input.
5. System Design Information
Page 34 of 63
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
IBM [ IBM ]
