Data Sheet
Preliminary
PowerPC® 750CXe RISC Microprocessor
Figure 4-8 provides the TRST timing diagram.
Figure 4-8. TRST Timing Diagram
TRST
5
Figure 4-9 provides the boundary-scan timing diagram.
Figure 4-9. Boundary-Scan Timing Diagram
TCK
7
6
Data Inputs
Input Data Valid
8
Data Outputs
Output Data Valid
9
Data Outputs
Figure 4-10 provides the test access port timing diagram.
Figure 4-10. Test Access Port Timing Diagram
TCK
10
11
TDI, TMS
Input Data (Valid)
12
Output Data (Valid)
TDO
13
TDO
TDO
Output Data (Invalid)
14
750cxe_DD3.1_Dev_3_gen_mkt.fm.1.5
April 8, 2004
Electrical and Thermal Characteristics
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