Data Sheet
PowerPC® 750CXe RISC Microprocessor
Preliminary
4.5.1 IEEE 1149.1 AC Timing Specifications
Table 4-9 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 4-7, Figure 4-8,
Figure 4-9, and Figure 4-10. The five JTAG signals are; TDI, TDO, TMS, TCK, and TRST.
Table 4-9. JTAG AC Timing Specifications (Independent of SYSCLK)
See Table 4-2 on page 7 for operating conditions.
Num
Characteristic
TCK frequency of operation
Min
0
Max
25
—
Unit
MHz
ns
Notes
1
2
TCK cycle time
40
15
0
TCK clock pulse width measured at +1.1V
TCK rise and fall times
—
ns
3
2
ns
4
4
Specification obsolete, intentionally omitted
TRST assert time
5
25
0
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
6
Boundary-scan input data setup time
Boundary-scan input data hold time
TCK to output data valid
7
13
–
2
8
3, 5
3, 4
9
TCK to output high impedance
TMS, TDI data setup time
3
19
—
—
12
9
10
11
12
13
14
0
TMS, TDI data hold time
15
2.5
3
TCK to TDO data valid
5
4
TCK to TDO high impedance
TCK to output data invalid (output hold)
0
–
Notes:
1. TRST is an asynchronous level sensitive signal. Guaranteed by design.
2. Non-JTAG signal input timing with respect to TCK.
3. Non-JTAG signal output timing with respect to TCK.
4. Guaranteed by characterization and not tested.
5. Minimum specification guaranteed by characterization and not tested.
Figure 4-7 provides the JTAG clock input timing diagram.
Figure 4-7. JTAG Clock Input Timing Diagram
1
2
2
TCK
3
VM
VM
VM
3
VM = Midpoint Voltage (+0.9V)
Electrical and Thermal Characteristics
Page 16 of 36
750cxe_DD3.1_Dev_3_gen_mkt.fm.1.5
April 8, 2004
IBM [ IBM ]
