Data Sheet
Preliminary
PowerPC® 750CXe RISC Microprocessor
Figure 4-4 provides the mode select input timing diagram for the PowerPC 750CXe.
Figure 4-4. Mode Select Input Timing Diagram
VIH
HRESET
10c
10c
11b
11b
MODE PINS
VIH = +1.24V
4.5 60x Bus Output AC Specifications
Table 4-8 provides the 60x bus output AC timing specifications for the PowerPC 750CXe as defined in
Figure 4-7 on page 16.
Table 4-8. 60x Bus Output AC Timing Specifications1,4,6 See Table 4-2 on page 7 for operating conditions.
1.8V Mode
Min.
2.5V Mode
Min.
Num
Characteristic
Unit Notes
Max.
2.20
Max.
2.20
12 SYSCLK to Output Driven (Output Enable Time)
13 SYSCLK to Output Valid
0.3
–
0.3
–
ns
ns
14 SYSCLK to Output Invalid (Output Hold)
0.500
0.400
ns
ns
ns
2
SYSCLK to Output High Impedance (all signals except
ARTRY)
15
–
2.5
3.0
–
2.5
3.0
16 SYSCLK to ARTRY high impedance before precharge
17 SYSCLK to ARTRY precharge enable
–
–
0.2tSYSCLK+1.0
0.2tSYSCLK+1.0
ns 2, 3, 5
tSYSCLK 3, 5
tSYSCLK 3, 5
18 Maximum delay to ARTRY precharge
1
2
1
2
19 SYSCLK to ARTRY high impedance after precharge
Notes:
1. All output specifications are measured from the midpoint voltage (0.8V) of the rising edge of SYSCLK to the midpoint voltage of the signal in question
defined in figure 4-5. Both input and output timings are measured at the pin. Timings are determined by design.
2. This minimum parameter assumes CL = 0pF.
3. tSYSCLK is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration of the parameter in question.
4. Output signal transitions are defined in figure 4-5.
5. Nominal precharge width for ARTRY is 1.0 tSYSCLK
.
6. Guaranteed by design and characterization, and not tested.
750cxe_DD3.1_Dev_3_gen_mkt.fm.1.5
April 8, 2004
Electrical and Thermal Characteristics
Page 13 of 36
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