Datasheet
CPC945 Bridge and Memory Controller
Preliminary
2.1.2 PCI Express Interface
The PCI Express interface enables attaching other PCIe devices to the CPC945. The PCI-based interface
has the following features:
• PCI Express root complex
• Configurable single port with selectable lane width of ×1, ×4, x8, or ×16 bit lanes at 2.5 GHz
• Includes PCI configuration space
2
2.1.3 I C Interfaces
2
The CPC945 has three I C interfaces for use in configuring the memory subsystem and other CPC945
components.
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• Two software-selectable master-only I C interfaces for use in configuring the memory subsystem
2
• One slave I C interface for processor interface configuration, power management, debugging, and diag-
nostic purposes
2.1.4 Interrupt Controller
The interrupt controller collects and distributes system interrupts from the PCI Express and HyperTransport
blocks. The controller has the following features:
• Up to 128 interrupt sources (120 available) are collected from the HyperTransport bridge and delivered to
up to four processors.
• Interrupt controller registers are directly mapped inside the CPC945 register space.
• Interrupt sources internal to the CPC945 are delivered directly to the interrupt controller.
2.1.5 Memory Controller
The memory controller supports the CPC945’s double data rate 2 (DDR2) SDRAM memory subsystem. It has
the following features:
• Supports up to eight 64/72-bit wide double-sided DDR2 registered or unregistered DIMMs arranged in a
128/144-bit wide data bus providing 64 bytes in four data beats, or 128-byte access in two sets of four
data beats. Note: Achieving maximum memory transfer rate (533 MTps) and driving eight ranks of mem-
ory simultaneously is not possible without incorporating external components such as data multiplexers
and buffers to redrive the address and data signals.
• Corrects random single errors and detects double errors with ×4 chip kill error correction for the main
memory array.
• Runs asynchronously from the processor interface at up to 533 MHz.
• Provides efficient 128-byte cache line fills through a wide data bus.
Overview
A15-6009-03
December 18, 2007 - IBM Confidential
Page 18 of 69
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