Datasheet
CPC945 Bridge and Memory Controller
Preliminary
The boot read only memory (ROM) is connected to an I/O device attached to the system through the Hyper-
2
Transport bus. The CPC945 includes two master-only I C interfaces for configuring the memory subsystem.
2
An I C slave interface connects the CPC945 northbridge to a single-chip microcontroller for power manage-
ment and processor interface configuration. A multiprocessor-capable interrupt controller collects and distrib-
utes system interrupts from the PCI Express and HyperTransport blocks.
The CPC945 is (recognized or treated) by software as the following elements:
• A processor interface to the PCI Express root complex
• A processor interface to the HyperTransport host bridge
• A memory controller
• An interrupt controller
• A set of control registers
1.3 Revision Register
The CPC945 has the following Revision Register values for the corresponding design revision levels.
Table 1-1. CPC945 Revision Register
Design Revision Level
DD 1.2
Revision Register Value
x‘0000 0042’
DD 2.0
x‘0000 0044’
1.4 Part Number Information
Figure 1-1. Part Number Legend
3C-1
IBM25CPC945CQ
PowerPC 970MP Family Bridge Chip
Design Revision Level
Package Type
Process Sort
Junction Temperature Range
Reliability Grade
Design Revision Level
Package Type
C = DD 1.2
D = DD 2.0
Q = Lead-free C4, lead-free BGA, flip chip plastic ball grid array (FC-PBGA)
with 2 mm lid
Reliability Grade
3 = Grade 3
Junction Temperature Range
B = 0 – 105°C
C = 0 – 90°C
Process Sort PSRO Values
-1 = 211 - 240 ns
-2 = 168 - 210 ns
-3 = 168 - 240 ns
General Information
A15-6009-03
December 18, 2007 - IBM Confidential
Page 14 of 69
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