Datasheet
Preliminary
CPC945 Bridge and Memory Controller
2. Overview
2.1 Functional Blocks
Figure 2-1. CPC945 Block Diagram
PowerPC 970MP
Processors 0,1
PowerPC 970MP
Processors 2,3
Two 1.3 V - 1.5 V Processor Interfaces
1250 MTps (Maximum)
(2.5 V)
(2.5 V)
I2C Slave
I2C Slave
PCIe
Root
16-bit PCI Express
1.5 V, 2500 MTps
I2C Masters
I2C Master
Interrupt
Controller
Processor Interrupts
Clocks, Resets,
System Support,
Power Management
and Test
128-bit plus ECC
1.8 V, 533 MTps (Maximum)
General
Control
Registers
DDR2 SDRAM
(8 DIMMs, 8 Ranks)
Memory
Controller
Power and Ground
1.5 V 533 MHz Core
(1.2 V)
HyperTransport
Bridge
16-bit HyperTransport
up to 1600 MTps
MTps: Million transfers per second
CPC945
2.1.1 Processor Interfaces
The CPC945 has interfaces for connecting to two dual-core PowerPC 970xx RISC microprocessors. Each
interface consists of two separate point-to-point processor buses, each providing separate inbound and
outbound buses. Each interface has the following features:
• 35-bit (logical)/44-bit (physical) multiplexed address/data (AD)
• 1-bit transfer handshake
• 2-bit snoop response bus
• Supports split transactions for reads and writes using a tagged packet-passing protocol
• Transaction reflecting and global snooping that ensure memory-to-cache coherency
• Processor bus that runs asynchronously from the CPC945 core
• Debug facility that generates logic analyzer triggers and stores transaction samples
A15-6009-03
Overview
December 18, 2007 - IBM Confidential
Page 17 of 69
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