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IBM25CPC945CQ3C-2 参数 Datasheet PDF下载

IBM25CPC945CQ3C-2图片预览
型号: IBM25CPC945CQ3C-2
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC, CMOS, PBGA1182,]
分类和应用:
文件页数/大小: 69 页 / 1861 K
品牌: IBM [ IBM ]
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Datasheet  
Preliminary  
CPC945 Bridge and Memory Controller  
1. General Information  
1.1 Features  
• Dual PowerPC 970MP and 970FX processor interface buses with cache coherency and snooping proto-  
cols supporting up to four processor cores  
• PCI Express® ×1, ×4, ×8, or ×16 interface  
• 128/144-bit, 533 megatransfers per second (MTps) double data rate 2 (DDR2) synchronous DRAM  
(SDRAM) controller and interface with error correction code (ECC)  
• 800 MHz (1600 MTps DDR) HyperTransport host bridge with 16-bit wide data interface and flash ROM  
support  
2
• One slave and two master I C interfaces  
• Interrupt controller  
• Point-to-point internal architecture provides high-speed, nonblocking performance  
• 40-bit physical memory address space  
• 1182-pin flip-chip plastic ball grid array (FC-PBGA) single chip implementation  
• Processor interface interconnection speed of up to 625 MHz (1250 Mbps double data rate)  
• Support for eight outstanding transactions per master  
• Support for read pipelining and write combining from the processor interface or peripheral component  
interconnect (PCI) bus  
• Support for read-around-write on the processor interface with PCI ordering  
• Support for eight 64/72-bit double-sided dual inline memory modules (DIMMs) arranged in pairs  
• PCI and HyperTransport transactions snooped on the processor interface  
• Power management support for the CPC945 northbridge through clock control  
• DMA address relocation table (DART) provides flexible I/O memory space relocation and consolidation  
1.2 Description  
The CPC945 is a frontside bus controller that is compatible with the PowerPC 970MP and PowerPC 970FX  
reduced instruction set computer (RISC) microprocessors.  
The CPC945 provides a 5-way interconnection among the following elements:  
Two PowerPC 970xx family processor interfaces  
• A DDR2 SDRAM memory subsystem  
• PCI Express bus  
• A HyperTransport host bridge  
A15-6009-03  
December 18, 2007 - IBM Confidential  
General Information  
Page 13 of 69  
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