Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
PCI I/O Specifications—100 MHz
Notes:
1. Output Valid from PCI_CLK
2. Input Setup to PCI_CLK
3. Input Hold from PCI_CLK
4. Output Valid from PCG_CLK
5. Input Setup to PCG_CLK
6. Input Hold from PCG_CLK
Input (ns)
Output Valid (ns)
Max
Signal
Notes
Setup
Hold
Min
Load (pf)
(T min)
(T min)
IS
IH
PCI-32 Interface @ 33 MHz
P_ADL31:00
P_CBE3:0
P_DEVSEL
P_FRAME
P_IRDY
7
0.5
2
11.2
50
1, 2, 3
P_PAR
P_PERR
P_SERR
P_STOP
P_TRDY
P_LOCK
nananana50
P_GNT0:3
P_MEMACK
P_REQ0:6
P_MEMREQ
PCI-64 Interface @ 66 MHz
G_ADH31:0
G_ADL31:0
G_CBE7:0
G_ACK64
nana 2
12.2
50
50
1
nanana11.2
12
1
0.5
0
nanana2,
3
nanananana2,
3
2
2
7.6
10
4, 5, 6
3.2
0
0
0
0
0
0
2
2
2
2
2
2
7.1
6.6
7.4
6.2
6.6
6.2
10
10
10
10
10
10
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4
G_REQ64
G_DEVSEL
G_FRAME
G_IRDY
2.3
4
3.6
4.5
G_LOCK
nananana10
G_PAR
3
0
0
0
0
0
0
2
2
2
2
2
2
6.6
6.8
6.5
6.7
6.8
6.7
10
10
10
10
10
10
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
G_PAR64
2.3
1.2
2
G_PERR
G_SERR
G_STOP
G_TRDY
G_GNT0:2
G_GNT4:7
G_GNT3
3.2
3.8
nana 2
6.6
6.2
10
4
4
nana 2
2
10
G_IDSEL
G_REQ0:7
0
0
nanana5,
nanana5,
6
6
4.5
53
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