Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
Signals Listed by Ball Assignment (Part 2 of 7)
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
G_ADL26
Ball
H01
Signal Name
G_ADL23
OV
E01
F01
G_ADL29
G01
DD
E02
E03
E04
E05
E06
E07
E08
E09
E10
G_ADL30
GND
F02
F03
F04
F05
F06
F07
F08
F09
F10
G_ADL28
G_ADL27
G_PERR
G02
G03
G04
G05
G06
G07
G08
G09
G10
G_ADL25
H02
H03
H04
H05
H06
H07
H08
H09
H10
G_ADL22
G_ADL21
G_ADL20
G_ADL19
G_ARB
OV
DD
SDCAS0
G_ADL24
GND
V
SDCAS1
DD
MDATA41
GND
MUX_CLKENA1
MDATA49
MDATA50
MDATA51
MDATA52
DLK
V
MUX_CLKENA2
WE0
DD
MDATA42
MDATA58
GND
OV
WE1
DD
V
MDATA43
MDATA59
DD
OV
E11
E12
E13
E14
E15
E16
E17
GND
F11
F12
F13
F14
F15
F16
F17
MDATA53
MDATA54
MDATA55
GND
G11
G12
G13
G14
G15
G16
G17
H11
H12
H13
H14
H15
H16
H17
MDATA65
GND
DD
MDATA44
MDATA45
MDATA46
MDATA47
MDATA48
GND
MDATA60
MDATA61
MDATA62
MDATA63
MDATA64
MDATA66
OV
DD
MDATA56
MDATA57
MADDR04
MDATA67
GND
OV
MADDR12
DD
V
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
MADDR02
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
MADDR05
MADDR06
MADDR07
MADDR08
MADDR09
PLL_RANGE1
P_IRDY
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
MADDR10
GND
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
DD
OV
MADDR13
PLL_TUNE1
P_LOCK
DD
MADDR03
GND
MADDR11
V
DD
IT1
P_ADL21
GND
P_ADL20
P_PAR
V
DD
IT2
P_MEMACK
P_MEMREQ
GPIO0
OV
GND
TDI
GPIO1
DD
XCVR_RD
TDO
XADR_LAT
FLASH_CE
FLASH_WE
FLASH_OE
OV
DD
29
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