Preliminary
IBM16M64644HGA
IBM16M32644HGA
IBM16M64734HGA
IBM16M32734HGA
32/64Mx64/72 1 or 2 Bank Registered DDR SDRAM Module
Input/Output Functional Description
Symbol
CK0
CK0
CKE0, CKE1
S0, S1
RAS, CAS, WE
V
REF
V
DDQ
BA0,1
Type
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
Supply
Supply
(SSTL)
—
Polarity
Function
The positive line of the differential pair of system clock inputs which drives the input to the on-
Positive
DIMM PLL. All the DDR SDRAM addr/cntl inputs are sampled on the rising edge of their asso-
Edge
ciated clocks.
Negative The negative line of the differential pair of system clock inputs which drives the input to the on-
Edge DIMM PLL.
Active
High
Active
Low
Active
Low
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deacti-
vating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation
to be executed by the SDRAM.
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity
Selects which SDRAM bank of four is activated.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when
sampled at the rising clock edge. In addition to the column address, AP is used to invoke auto-
precharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is dis-
abled.
During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to control which
bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0
or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge.
Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM config-
urations.
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write
latency of one clock once the write command is registered into the SDRAM.
Power and ground for the DDR SDRAM input buffers and core logic
A0 - A9, A11,
A12, A10/AP
(SSTL)
—
DQ0 - DQ63,
CB0 - CB7
DM0-DM8
V
DD
, V
SS
DQS0-DQS8
RESET
SA0 - 2
SDA
SCL
V
DDSPD
(SSTL)
(SSTL)
Supply
—
Active
High
Negative
(SSTL) and Posi- Data strobe for input and output data
tive Edge
(LVC-
MOS)
Active
Low
—
—
—
Supply
Asynchronously forces all register outputs low when RESET is low. This signal can be used
during power up to ensure CKE0/1 are low and SDRAM DQS are Hi-Z.
These signals are tied at the system planar to either V
SS
or V
DD
to configure the serial SPD
EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must
be connected from the SDA bus line to V
DD
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected from the SCL bus time to V
DD
to act as a pullup.
Serial EEPROM positive power supply.
19L7358.H02502
3/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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