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IBM16M64734HGA-10HT 参数 Datasheet PDF下载

IBM16M64734HGA-10HT图片预览
型号: IBM16M64734HGA-10HT
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM Module, 64MX72, 0.8ns, CMOS, GOLD CONTACTS, DIMM-184]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 28 页 / 545 K
品牌: IBM [ IBM ]
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IBM16M64644HGA  
IBM16M64734HGA  
IBM16M32644HGA  
IBM16M32734HGA  
Preliminary  
32/64Mx64/72 1 or 2 Bank Registered DDR SDRAM Module  
Serial Presence Detect (Part 2 of 3)  
Serial PD Data Entry  
Byte #  
Description  
SPD Entry Value  
N/A  
Notes  
(Hexadecimal)  
Maximum Data Access Time (t ) from Clock at CLX-1 (CL =  
AC  
26  
00  
1.5)  
Minimum Row Precharge Time (t  
)
27  
28  
29  
20.0ns  
15.0ns  
50  
3C  
50  
RP  
Minimum Row Active to Row Active Delay (t  
)
RRD  
Minimum RAS to CAS Delay (t  
)
20.0ns  
50.0ns  
RCD  
PC200  
32  
2D  
40  
C0  
A0  
C0  
A0  
60  
A0  
60  
A0  
00  
00  
cc  
Minimum Active to Precharge Time (t  
)
30  
RAS  
PC266B  
45.0ns  
31 Module Bank Density - 32Mx64, x72  
256MB  
1.2ns  
PC200  
PC266B  
PC200  
32 Address and Command Setup Time before Clock  
33 Address and Command Hold Time after Clock  
34 Data/Data Mask Input Setup Time before Clock  
35 Data/Data Mask Input Hold Time after Clock  
1.0ns  
1.2ns  
PC266B  
PC200  
1.0ns  
8
0.6ns  
PC266B  
PC200  
1.0ns  
0.6ns  
PC266B  
1.0ns  
36-61 Reserved  
Undefined  
0
62 SPD Revision  
63 Checksum for Bytes 0 - 62  
64-71 Manufacturers’ JEDEC ID Code  
Checksum Data  
IBM  
2
A400000000000000  
91  
53  
Toronto, Canada  
Vimercate, Italy  
72 Module Manufacturing Location  
ASCII ‘16M32644HG”R” 31364D33323634344847rr  
-10HT 2D313048542020  
ASCII ‘16M32734HG”R” 31364D33323733344847rr  
-10HT 2D313048542020  
ASCII ‘16M64644HG”R” 31364D36343634344847rr  
-10HT 2D313048542020  
ASCII ‘16M64734HG”R” 31364D36343733344847rr  
-10HT 2D313048542020  
ASCII ‘16M32644HG”R” 31364D33323634344847rr  
-8ET 2D384554202020  
ASCII ‘16M32734HG”R” 31364D33323733344847rr  
-8ET 2D384554202020  
ASCII ‘16M64644HG”R” 31364D36343634344847rr  
-8ET 2D384554202020  
ASCII ‘16M64734HG”R” 31364D36343733344847rr  
32Mx64  
32Mx72  
64Mx64  
64Mx72  
32Mx64  
32Mx72  
64Mx64  
64Mx72  
PC200  
73-90 Module Part Number  
3, 4  
PC266B  
-8ET  
2D384554202020  
91-92 Module Revision Code  
“R” plus ASCII blank  
Year/Week Code  
rr20  
4
93-94 Module Manufacturing Date  
yyww  
5, 6  
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (that is, Device CL [clock  
cycles] + 1 = DIMM CAS latency).  
2. cc = Checksum Data byte, 00-FF (Hex).  
3. “R” = Alphanumeric revision code, A-Z, 0-9.  
4. rr = ASCII coded revision code byte “R”.  
5. ww = Binary coded decimal week code, 01-52 (Decimal) ‘ 01-34 (Hex).  
6. yy = Binary coded decimal year code, 00-99 (Decimal) ‘ 00-63 (Hex).  
7. ss = Serial number data byte, 00-FF (Hex).  
8. Setup and hold values assume a 1 Volt/ns slew rate.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
19L7358.H02502  
3/00  
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