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IBM16M64734HGA-10HT 参数 Datasheet PDF下载

IBM16M64734HGA-10HT图片预览
型号: IBM16M64734HGA-10HT
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM Module, 64MX72, 0.8ns, CMOS, GOLD CONTACTS, DIMM-184]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 28 页 / 545 K
品牌: IBM [ IBM ]
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IBM16M32644HGA  
IBM16M32734HGA  
IBM16M64644HGA  
IBM16M64734HGA  
32/64Mx64/72 1 or 2 Bank Registered DDR SDRAM Module  
Preliminary  
Serial Presence Detect (Part 1 of 3)  
Serial PD Data Entry  
Byte #  
Description  
SPD Entry Value  
Notes  
(Hexadecimal)  
0
1
2
3
4
Number of Serial PD Bytes Written during Production  
Total number of bytes in Serial PD Device  
Fundamental Memory Type  
128  
80  
08  
07  
0D  
0A  
01  
02  
256  
SDRAM DDR  
Number of Row Addresses on Assembly  
Number of Column Addresses on Assembly  
13  
10  
1
32Mx64, 72  
5
Number of Physical Banks on DIMM  
64Mx64, 72  
2
32M,  
x64  
x72  
4000  
4800  
64Mx64  
6-7 Data Width of Assembly  
32M,  
64Mx72  
8
9
Voltage Interface Level of this Assembly  
SSTL 2.5V  
8.0ns  
04  
80  
PC200  
PC266B  
PC200  
SDRAM Device Cycle Time at Maximum CL (CLX  
= 2.5)  
1
7.5ns  
0.8ns  
80  
SDRAM Device Access Time from Clock at  
CL=2.5  
10  
PC266B  
0.75ns  
32M,  
Non-parity  
00  
02  
64Mx64  
11 DIMM Configuration Type  
32M,  
64Mx72  
ECC  
7.8µs/SR  
12 Refresh Rate/Type  
82  
08  
08  
13 Primary SDRAM Device Width  
14 Error Checking SDRAM Device Width  
x8  
x8  
SDRAM Device Attributes: Minimum Clock Delay, Random Col-  
umn Access  
15  
1 Clock  
01  
16 SDRAM Device Attributes: Burst Lengths Supported  
17 SDRAM Device Attributes: Number of Device Banks  
18 SDRAM Device Attributes: CAS Latency  
19 SDRAM Device Attributes: CS Latency  
2, 4, 8  
0E  
04  
0C  
01  
02  
4
2, 2.5  
0
20 SDRAM Device Attributes: WE Latency  
1
Registered with PLL,  
Differential clock  
21 SDRAM Module Attributes  
26  
00  
VDD ± 0.2V  
22 SDRAM Device Attributes: General  
PC200  
10.0ns  
8.0ns  
A0  
80  
23 Minimum Clock Cycle at CLX-0.5 (CL = 2)  
1
PC266B  
PC200  
± 0.8ns  
80  
Maximum Data Access Time (t ) from Clock at  
AC  
24  
CLX-0.5 (CL = 2)  
PC266B  
± 0.75ns  
75  
00  
25 Minimum Clock Cycle Time at CLX-1 (CL = 1.5)  
N/A  
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (that is, Device CL [clock  
cycles] + 1 = DIMM CAS latency).  
2. cc = Checksum Data byte, 00-FF (Hex).  
3. “R” = Alphanumeric revision code, A-Z, 0-9.  
4. rr = ASCII coded revision code byte “R”.  
5. ww = Binary coded decimal week code, 01-52 (Decimal) ‘ 01-34 (Hex).  
6. yy = Binary coded decimal year code, 00-99 (Decimal) ‘ 00-63 (Hex).  
7. ss = Serial number data byte, 00-FF (Hex).  
8. Setup and hold values assume a 1 Volt/ns slew rate.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
19L7358.H02502  
3/00  
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