IBM0612404GT3B
IBM0612804GT3B
128Mb Double Data Rate Synchronous DRAM
Advance Rev 0.2
Write to Precharge: Minimum DQSS, Odd Number of Data (1 bit Write), Interrupting
(Burst Length = 4 or 8)
T1
T2
T3
T4
T5
T6
CK
CK
Write
NOP
NOP
NOP
PRE
NOP
Command
t
WR
BA a, COL b
BA (a or all)
Address
t
t
(min)
RP
2
DQSS
DQS
DQ
DI a-b
1
1
3
4
4
DM
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 1 data element is written.
is referenced from the first positive CK edge after the last desired data in pair.
t
WR
The Precharge command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.
3 = This bit is correctly written into the memory array if DM is low.
4 = These bits are incorrectly written into the memory array if DM is low.
Don’t Care
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Use is further subject to the provisions at the end of this document.
06K0566.F39350
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