IBM0612404GT3B
IBM0612804GT3B
Advance Rev 0.2
128Mb Double Data Rate Synchronous DRAM
Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8)
T1
T2
T3
T4
T5
T6
CK
CK
Write
NOP
NOP
NOP
PRE
NOP
Command
t
WR
BA (a or all)
BA a, COL b
Address
t
t
(nom)
RP
DQSS
2
DQS
DQ
DI a-b
3
3
1
1
DM
DI a-b = Data In for bank a, column b.
An interrupted burst is shown, 2 data elements are written.
1 subsequent element of data in is applied in the programmed order following DI a-b.
is referenced from the first positive CK edge after the last desired data in pair.
t
WR
The Precharge command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.
3 = These bits are incorrectly written into the memory array if DM is low.
Don’t Care
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06K0566.F39350
5/00
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