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IBM04368CBLBC-28 参数 Datasheet PDF下载

IBM04368CBLBC-28图片预览
型号: IBM04368CBLBC-28
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 256KX36, 1.8ns, CMOS, PBGA153, BGA-153]
分类和应用: 时钟静态存储器内存集成电路
文件页数/大小: 24 页 / 314 K
品牌: IBM [ IBM ]
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IBM04368CBLBC  
IBM04188CBLBC  
8Mb (256K x 36 & 512K x 18) SRAM  
Instruction Set  
Code  
000  
001  
010  
011  
100  
101  
110  
111  
Instruction  
SAMPLE-Z  
IDCODE  
Notes  
1
2
1
5
4
5
5
3
SAMPLE-Z  
PRIVATE  
SAMPLE  
PRIVATE  
PRIVATE  
BYPASS  
1. Places DQs in High-Z in order to sample all input data regardless of other SRAM inputs.  
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.  
3. BYPASS register is initialized to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded  
TDI when exiting the Shift DR state.  
4. SAMPLE instruction does not place DQs in High-Z.  
5. PRIVATE is reserved for the exclusive use of IBM. Invoking this instruction will cause improper SRAM functionality.  
This part has not been designed to comply with the following sections of IEEE 1149.1:  
• 7.2.1.b, e  
• 7.7.1.a–f  
• 10.1.1.b, e  
• 10.7.1.a–d  
CBLBC_ds.fm.00  
June 7, 2002  
Page 18 of 24  
 
 
 
 
 
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