IBM04368CBLBC
IBM04188CBLBC
8Mb (256K x 36 & 512K x 18) SRAM
IEEE 1149.1 TAP and Boundary Scan
The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os
and printed circuit-board traces or other components. There is no multiplexer in the path from the I/O pins to
the RAM core.
In conformance with IEEE standard 1149.1, the SRAM contains a TAP controller, instruction register, bound-
ary scan register, bypass register, and ID register.
The TAP controller has a standard 16-state machine that resets internally upon power-up; therefore, a TRST
signal is not required.
Signal List:
• TCK: Test Clock
• TMS: Test Mode Select
• TDI: Test Data In
• TDO: Test Data Out
JTAG Recommended DC Operating Conditions (TA = 0 to 85°C)
Symbol
VIH1
Parameter
Min.
2.0
-0.3
2.1
—
Typ.
—
Max.
Units
Notes
VDD + 0.3V
JTAG Input High Voltage
JTAG Input Low Voltage
JTAG Output High Level
JTAG Output Low Level
V
V
V
V
VIL1
VOH1
VOL1
—
0.8
—
—
1
2
—
0.2
1. OH1 = -2mA at 2.1V
2. OL1 = +2mA at 0.2V
JTAG AC Test Conditions (TA = 0 to +85°C, VDD = 2.5V 5%)
Symbol
VIH1
Parameter
Conditions
Units
V
Notes
Input Pulse High Level
Input Pulse Low Level
Input Rise Time
2.0
0.0
2.0
2.0
1.0
VIL1
tR1
V
ns
ns
V
tF1
Input Fall Time
Input and Output Timing Reference Level
1
1. See AC Test Loading on page 11.
CBLBC_ds.fm.00
June 7, 2002
Page 15 of 24
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