IBM04368CBLBC
IBM04188CBLBC
8Mb (256K x 36 & 512K x 18) SRAM
Scan Register Definition
Register Name
Instruction
Bypass
Bit Size x18
Bit Size x36
Notes
3
1
3
1
ID
32
49
32
68
Boundary Scan
1, 2
1. The boundary-scan chain consists of the following bits:
•
•
•
•
36 or 18 bits for data inputs depending on x36 or x18 configuration
19 bits for SA0–SA18 for x36, 20 bits for SA0–SA19 for x18
4 or 2 bits for CQ and CQ clocks depending on x36 or x18 configuration
9 bits for CK, CK, ZQ, LBO, B1, B2, B3, MODE and G
2. CK and CK clocks connect to a differential receiver that generates a single-ended clock signal. This signal and its inverted value
are used for boundary-scan sampling. CQ and CQ clocks are sampled from the CK and CK boundary scan register inputs.
ID Register Definition
Field Bit Number and Description
Part
Revision Number
(31:28)
Device Density and
Configuration (27:18)
Vendor Definition
(17:12)
Manufacture JEDEC
Code (11:1)
Start
Bit(0)
xxxx1
xxxx1
512K x 18
256K x 36
1011110011
1011010100
101101
101101
000101001001
000101001001
1
1
1. For IBM internal use.
1.
CBLBC_ds.fm.00
June 7, 2002
Page 17 of 24
IBM [ IBM ]
