IBM04368CBLBC
IBM04188CBLBC
8Mb (256K x 36 & 512K x 18) SRAM
AC Characteristics (TA = 0 to +85°C, VDD = 2.5V 5%)
-25
-28
-30
-35
Symbol
Parameter
Units Notes
Min. Max. Min. Max. Min. Max. Min Max
tKHKH
tKHKL
tKLKH
tAVKH
tKHAX
tBVKH
tKHBX
tDVKH
tKHDX
tINPW
Cycle Time
2.5
1.2
1.2
0.4
2.8
1.2
1.2
0.4
3.0
1.4
3.5
1.6
1.6
0.5
0.5
0.5
0.5
0.3
0.3
1.6
ns
ns
ns
Clock High Pulse Width
Clock Low Pulse Width
Address Setup Time
1.4
0.5
ns
ns
ns
ns
1, 2,
Address Hold Time
0.4
0.4
0.5
1, 2, 6
1, 2, 6
1, 2, 6
Function Control (B1, B2, B3) Setup Time
Function Control (B1, B2, B3) Hold Time
Data In Setup Time
0.4
0.4
0.5
0.4
0.4
0.5
0.21
0.21
1.0
0.25
0.25
1.0
0.25
0.25
1.2
ns 1, 2, 3, 6
Data In Hold Time
ns
1,2,3,6
7
Input Pulse Width
tKHKL tKHKL tKHKL tKHKL tKHKL tKHKL tKHKL tKHKL
-0.1 +0.1 -0.1 +0.1 -0.1 +0.1 -0.1 +0.1
tCHCL
tCLCH
tKXCV
Echo Clock (CQ) High Pulse Width
Echo Clock (CQ) Low Pulse Width
ns
ns
ns
1, 3, 6
1, 3, 6
1, 4, 6
tKLKH tKLKH tKLKH tKLKH tKLKH tKLKH tKLKH tKLKH
-0.1 +0.1 -0.1 +0.1 -0.1 +0.1 -0.1 +0.1
Clock (CK) crossing to Echo clock (CQ) Valid - slow
corner
0.8
1.8
0.8
1.8
0.8
1.7
0.8
1.8
tKXQV
tKXQZ
tKXQLZ
Clock (CK) crossing to Output Valid
0.8
0.8
0.8
1.8
1.8
1.8
0.8
0.8
0.8
1.8
1.8
1.8
0.8
0.8
0.8
1.7
1.7
1.7
0.8
0.8
0.8
1.8
1.8
1.8
ns
ns
ns
1, 6
1, 6
1, 6
Clock (CK) crossing to Output High-Z
Clock (CK) crossing to Output Active
Echo Clock (CQ) Valid to Output Valid Tracking
tQVTRK
-0.2
-0.2
-0.2
0.2 -0.2
0.2 -0.2
0.2 -0.2
0.2
0.2
0.2
-0.2
-0.2
-0.2
0.2
0.2
0.2
-0.2
-0.2
-0.2
0.2
0.2
0.2
ns 1, 3, 5, 6
(tKXCV - tKXQV
)
Echo Clock (CQ) Valid to Output High-Z Tracking
tQZTRK
ns
ns
1,3,5,6
1,3,5,6
(tKXCV - tKXQZ
)
Echo Clock (CQ) Valid to Output Active Tracking
tQLZ-
TRK
(tKXCV - tKXQLZ
)
tGHQZ
Output Enable (G) High to High-Z
1.7
1.7
—
1.7
1.7
2.0
2.0
2.0
2.0
ns
ns
3
3
tGLQV
Output Enable (G) Low to Output Valid
0.5
1. See AC Test Loading on page 11. To guarantee AC timing specifications, AC test conditions must be met.
2. To guarantee AC characteristics; VIH, VIL, Trise, and Tfall of inputs and clocks must be within 20% of each other. If these conditions
are not met, then setup time is measured from clock crossing to inputs at their switched VIHAC, VILAC levels, and hold time is mea-
sured from clock crossing to inputs switching out of their valid VIHAC, VILAC levels.
3. These parameters may not be tested at the values shown in this table, and may only be guaranteed by design.
4. Echo clock (CQ) Valid refers to CQ and CQ rising and falling edges.
5. The tracking between echo-clock access times and DQ access times is across all cycle boundaries for any given SRAM address
and function pattern.
6. CK and CK clocks must be used differentially in order to meet specification.
7. Can not have an input pulse width that consists of |minimum setup time| + |minimum hold time|.
CBLBC_ds.fm.00
June 7, 2002
Page 12 of 24
IBM [ IBM ]
