IBM04368CBLBC
IBM04188CBLBC
8Mb (256K x 36 & 512K x 18) SRAM
Clock Truth Table
CK
B1 (n)
B2 (n)
H
B3 (n)
H
DQ (n)
X
DQ (n+1)
DQ (n+1.5)
Mode
Read Cycle SDR
Previous Data
Held
DOUT 0-35
L
L→H
DOUT 0-35a
DIN 0-35
DOUT 0-35b
L
L
H
L
L
H
L
X
X
X
X
Read Cycle DDR
L→H
L→H
L→H
L→H
L→H
X
Write Cycle SDR
DIN 0-35a
DIN 0-35b
High-Z
L
L
Write Cycle DDR
H
H
L
X
X
High-Z
NOP (Deselect) Cycle
Continue Burst Operation
H
Output Enable Truth Table
Operation (n, n+1)
G (n)
G (n+1)
DQ (n)
DQ (n+1)
DOUT 0-35
Read
Read
Write
NOP
L
H
L
L
H
L
X
High-Z
High-Z
High-Z
High-Z
X
X
L
L
Absolute Maximum Ratings
Symbol
VDD
Parameter
Rating
Units
V
Notes
Power Supply Voltage
Input Voltage
-0.5 to 2.825
-0.5 to 3.0
-0.5 to 2.825
0 to +85
1
1
1
1
VIN
VOUT
TA
V
Output Voltage
V
Operating Temperature
Junction Temperature
Storage Temperature
Short Circuit Output Current
°C
°C
°C
mA
TJ
0 to +110
-55 to +125
25
TSTG
IOUT
1
1
1. Stresses greater than those listed under “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods can affect reliability.
CBLBC_ds.fm.00
June 7, 2002
Page 8 of 24
IBM [ IBM ]
