IBM04368CBLBC
IBM04188CBLBC
8Mb (256K x 36 & 512K x 18) SRAM
Recommended DC Operating Conditions (TA = 0 to 85°C)
Symbol
VDD
Parameter
Min.
2.5V - 5%
1.4
Typ.
2.5
1.8
Max.
2.5V + 5%
1.9
Units
V
Notes
1
Supply Voltage
VDDQ
VIH
Output Driver Supply Voltage
Input High Voltage
V
1
VREF + 0.1
VDDQ + 0.3
VREF - 0.1
V
1, 2
1, 3
1, 6
1, 4
1, 5
1
VIL
Input Low Voltage
-0.3
0.68
-0.3
0.1
V
VREF
Input Reference Voltage
Clocks Signal Voltage
.9
1.0
V
VIN - CLK
VDIF - CLK
VCM - CLK
VDDQ + 0.3
V
VDDQ + 0.6
Differential Clocks Signal Voltage
Clocks Common Mode Voltage
V
0.55
0.9
V
1. All voltages referenced to VSS. All VDD, VDDQ and VSS pins must be connected.
2. VIH(Max) DC = VDDQ + 0.3V, VIH(Max) AC = VDDQ + 0.85 (pulse width ≤ 2ns).
3. VIL(Min) DC = -0.3V, VIL(Min) AC = -1.5V (pulse width ≤ 2ns).
4. VIN-CLK specifies the maximum allowable DC excursions of each differential clock (CK, CK).
5. VDIF-CLK specifies the minimum clock differential voltage required for switching.
6. Peak-to-peak AC component superimposed on VREF may not exceed 5% of VREF.
DC Electrical Characteristics (TA= 0 to +85°C, VDD = 2.5V 5%)
Symbol
Parameter
Min.
Max.
750
640
510
540
470
390
Units
Notes
1
-25
-30
-40
-25
-30
-40
x36
x18
mA
mA
Average Power Supply Operating Current
IDD
(IOUT = 0, VIN = VIH or VIL)
1
1
Power Supply Standby Current
ISB
150
+2
mA
SS = VIH, all other inputs = VIH or VIL, IOUT = 0
Input Leakage Current, any input
ILI
-2
µA
(VIN = VSS or VDDQ
)
Output Leakage Current
(VOUT = VSS or VDDQ, DQ in High-Z)
ILO
VOH
VOL
-5
+5
µA
V
Output “High” Level Voltage (IOH = -6mA)
VDDQ - 0.4
VSS
VDDQ
2
2
Output “Low” Level Voltage
(IOL = +6mA)
VSS + 0.4
V
JTAG Leakage Current
ILIJTAG
-70
+10
3
µA
(VIN = VSS or VDD
)
1.
IOUT = Device Output Current.
2. Minimum Impedance Output Driver.
3. For JTAG Inputs only.
CBLBC_ds.fm.00
June 7, 2002
Page 9 of 24
IBM [ IBM ]
