IBM04368CBLBC
IBM04188CBLBC
8Mb (256K x 36 & 512K x 18) SRAM
Programmable Impedance Output Driver DC Electrical Characteristics
(TA = 0 to +85°C, VDD = 2.5V 5%)
Symbol
VOH
Parameter
Min.
Max.
Units
V
Notes
1, 3
VDDQ / 2
VDDQ
Output High Voltage
Output Low Voltage
VOL
VDDQ / 2
Vss
V
2, 3
1. IOH = (VDDQ / 2) / (RQ / 5) 15% @ VOH = VDDQ / 2 (for: 175Ω ≤ RQ ≤ 350Ω)
2. OL = (VDDQ / 2) / (RQ / 5) 15% @ VOL = VDDQ / 2 (for: 175Ω ≤ RQ ≤ 350Ω)
I
3. Parameter tested with RQ = 250Ω and VDDQ = 1.8V
PBGA Thermal Characteristics
Symbol
Parameter
Thermal Resistance Junction to Case
Rating
1.6
Units
°C/W
RΘJC
Capacitance (TA = 0 to +85°C, VDD = 2.5V 5%, f = 1MHz)
Symbol
CIN
Parameter
Test Condition
VIN = 0V
Max.
Units
Input Capacitance
Data I/O Capacitance (DQ0–DQ35)
4
5
pF
pF
COUT
VOUT = 0V
AC Input Characteristics (TA= 0 to +85°C, VDD = 2.5V 5%)
Symbol
IH (ac)
Parameter
AC Input Logic High
Min.
Max.
Units
mV
Notes
3, 4
3, 4
2, 3
1
V
VREF + 400
VIL (ac)
VDIF (ac)
VREF (ac)
VREF - 400
AC Input Logic Low
mV
Clock Input Differential Voltage
VREF Peak-to-Peak AC Voltage
800
mV
5% VREF (DC)
mV
1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF
2. SRAM performance is a function of clock input differential voltage (VDIF).
.
3. To guarantee AC characteristics; VIH,VIL,Trise and Tfall of the inputs and clocks must be within 20% of each other. If these condi-
tions are not met then:
•
•
Setup time is measured from clock crossing to inputs at their switched VIHAC and VILAC levels.
Hold time is measured from clock crossing to inputs switching out of their valid VIHAC and VILAC levels.
4. See AC Input Definition on page 11.
CBLBC_ds.fm.00
June 7, 2002
Page 10 of 24
IBM [ IBM ]
