IBM04184BSLAC
IBM04364BSLAC
Preliminary 256K x 18 & 128K x 36 Standard Write SRAM
Clock Truth Table
K
ZZ
L
SS
L
SW
H
L
SBWa
SBWb
SBWc
SBWd
DQ (n)
DQ (n+1)
Mode
DOUT 0-35
X
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
X
X
X
Read Cycle All Bytes
Write Cycle 1st Byte
Write Cycle 2nd Byte
Write Cycle 3rd Byte
Write Cycle 4th Byte
L→H
L→H
L→H
L→H
L→H
L→H
DIN 0-8
DIN 9-17
DIN 18-26
DIN 27-35
DIN 0-35
L
L
L
L
L
H
H
H
L
L
L
H
H
L
L
L
H
L
L
L
L
L
L
L
H
X
X
L
H
X
X
L
H
X
X
L
H
X
X
X
X
Write Cycle All Bytes
Abort Write Cycle
Deselect Cycle
Sleep Mode
High-Z
High-Z
High-Z
L→H
L→H
X
L
H
X
X
X
X
H
High-Z
Output Enable Truth Table
Operation
Read
G
L
DQ
DOUT 0-35
Read
H
X
X
X
High-Z
High-Z
High-Z
High-Z
Sleep (ZZ=H)
Write (SW=L)
Deselect (SS=H)
Absolute Maximum Ratings
Symbol
VDD
Parameter
Power Supply Voltage
Rating
-0.5 to 3.9
VDD
Units
V
Notes
1
1
1
1
1
1
1
VDDQ
VIN
VOUT
TJ
TSTG
IOUT
Output Power Supply Voltage
Input Voltage
V
-0.5 to VDD+0.5
-0.5 to VDD+0.5
0 to +110
V
Output Voltage
V
Operating Temperature
Storage Temperature
Short Circuit Output Current
°C
°C
mA
-55 to +125
25
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
75H4340
July 25, 2000
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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