IBM04184BSLAC
IBM04364BSLAC
256K x 18 & 128K x 36 Standard Write SRAM
Preliminary
x36 BGA Bump Layout (Top View)
1
2
3
4
5
6
7
VDDQ
VDDQ
A
B
C
SA5
NC
SA7
SA8
SA9
VSS
NC
NC
VDD
SA16
SA11
SA10
VSS
SA14
NC
NC
NC
NC
NC
SA6
SA15
D
E
F
DQc18
DQc20
VDDQ
DQc19
DQc21
DQc22
DQc24
DQc26
VDD
NC
SS
G
DQb10
DQb12
DQb13
DQb15
DQb17
VDD
DQb9
DQb11
VDDQ
VSS
VSS
VSS
VSS
G
H
DQc23
DQc25
VDDQ
SBWc
VSS
NC
NC
VDD
SBWb
VSS
DQb14
DQb16
VDDQ
J
NC
VSS
SBWd
VSS
NC
VSS
SBWa
VSS
K
L
DQd34
DQd32
VDDQ
DQd35
DQd33
DQd31
K
DQa8
DQa6
DQa4
DQa7
DQa5
VDDQ
NC
SW
M
VSS
VSS
VSS
VSS
N
P
R
T
DQd29
DQd27
DQd30
DQd28
SA0
SA1
VDD
DQa3
DQa1
DQa2
DQa0
NC
NC
SA4
NC
M1*
SA3
TDI
M2*
SA13
TDO
SA12
NC
NC
ZZ
SA2
TCK
VDDQ
VDDQ
U
TMS
NC
Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VSS and VDD, respectively.
x18 BGA Bump Layout (Top View)
1
2
3
4
5
6
7
VDDQ
NC
VDDQ
NC
A
B
C
D
E
F
SA5
NC
SA7
SA8
SA9
VSS
VSS
NC
NC
SA16
SA11
SA10
VSS
SA14
NC
VDD
NC
SA6
SA15
NC
DQb9
NC
NC
DQb12
NC
NC
SS
G
DQa1
NC
NC
VSS
DQa2
VDDQ
VDDQ
VSS
VSS
VSS
VSS
DQa4
NC
G
H
J
NC
DQb15
NC
SBWb
VSS
NC
NC
VDD
DQa5
NC
DQb16
VDDQ
DQa8
VDD
NC
VDD
VDDQ
NC
VSS
VSS
VSS
VSS
VSS
NC
VSS
K
L
NC
DQb17
NC
K
DQa7
NC
DQb14
VDDQ
NC
SBWa
VSS
DQa6
NC
VDDQ
M
N
P
R
T
DQb13
NC
SW
SA0
SA1
VDD
NC
VSS
DQb11
NC
DQa3
NC
NC
VSS
DQb10
SA4
DQa0
NC
NC
M1
SA3
TDI
M2
SA13
SA12
NC
NC
ZZ
SA2
SA17
TDO
VDDQ
VDDQ
U
TMS
TCK
Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VSS and VDD respectively.
75H4340
July 25, 2000
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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