IBM04184BSLAC
IBM04364BSLAC
256K x 18 & 128K x 36 Standard Write SRAM
Preliminary
SRAM Features
Standard Write
In Standard Write function, write data must be registered in the same cycle as addresses and controls.
Mode Control
Mode control pins M1 and M2 are used to select four different JEDEC standard read protocols. This SRAM
only supports the single clock pipeline (M1 = V , M2 = V ) protocol. Mode control inputs must be set with
SS
DD
power up and must not change during SRAM operation.
Power Down Mode
Power Down mode, or “Sleep mode,” is accomplished by switching asynchronous signal ZZ high. When pow-
ering the SRAM down, inputs must be dropped first and V must be dropped before or simultaneously with
DDQ
V
.
DD
Power-Up Requirements
To guarantee the optimum internally regulated supply voltage, the SRAM requires 4µs of power-up time after
V
reaches its operating range. V must be powered up before or simultaneously with V . Inputs must
DD
DD
DDQ
be powered up after V
. V
should not exceed V supply by more than 0.4V during power up.
DDQ
DDQ DD
Sleep Mode Operation
Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin HIGH. During Sleep mode, all
other inputs are ignored and outputs are brought to a High-Z state. Sleep mode current and output High Z are
guaranteed after the specified sleep mode enable time. During Sleep mode, the array data contents are pre-
served. Sleep mode must not be initiated until after all pending operations have completed, as any pending
operation is not guaranteed to properly complete after Sleep mode is initiated. Sense amp data is lost. Nor-
mal operation can be resumed by bringing ZZ low, but only after specified Sleep mode recovery time.
75H4340
July 25, 2000
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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