.
IBM04184BSLAC
IBM04364BSLAC
Preliminary 256K x 18 & 128K x 36 Standard Write SRAM
Features
• 256K x 18 and 128K x 36 organizations
• CMOS technology
• Synchronous pipeline mode of operation with
standard write
• Single Clock compatible with LVTTL levels
• Byte Write capability and Global Write Enable
• +3.3V power supply. Separate output power
supply and ground
• Registered addresses, write enables, synchro-
nous select, and data ins
• Common I/O
AND
LVTTL I/O compatible
• 7 x 17 Bump Ball Grid Array package with
SRAM JEDEC Standard Pinout and Boundary
Scan order.
• Registered outputs
• Asynchronous Output Enable and Power Down
inputs
• Boundary Scan using limited set of JTAG 1149.1
functions
Description
IBM0418BSLAC and IBM0436BSLAC (Rev C part
numbers) are 4Mb high performance CMOS Syn-
chronous Static Random Access Memorie
S
which
operate in Pipeline Mode. These are versatile, wide
I/O SRAM
S
which achieve 7ns cycle times. K clock
is used to initiate the read/write operation and all
internal operations are self-timed. At the rising edge
of the K Clock, all Addresses, Write-Enables, Sync
Select, and Data Ins are registered internally. Data
Outs are updated from output registers off the next
rising edge of the K Clock. Data Ins are registered in
the same cycle as the write controls. These devices
operate with a +3.3V power supply and have an
optional +2.5V or 3.3V output power supply, and are
compatible with LVTTL I/O interfaces.
75H4340
July 25, 2000
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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