IBM041811TLAB
IBM043611TLAB
32K x 36 & 64K x 18 SRAM
Preliminary
IEEE 1149.1 TAP and Boundary Scan
The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os
and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the
RAM core.
In conformance with IEEE std. 1149.1, the SRAM contains a TAP controller, Instruction register, Boundary
Scan register, Bypass register, and ID register.
The TAP controller has a standard 16-state machine that resets internally upon power up; therefore, TRST
signal is not required.
Signal List
• TCK: Test Clock
• TMS: Test Mode Select
• TDI: Test Data In
• TDO: Test Data Out
Caution: TCK, TMS, TDI inputs must be biased to a valid logic level, even if JTAG is not used.
JTAG Recommended DC Operating Conditions (TA = 0 to 70°C)
Parameter
JTAG Input High Voltage
JTAG Input Low Voltage
JTAG Output High Level
JTAG Output Low Level
JTAG Input Leakage Current
Symbol
Min.
2.2
-0.3
2.4
—
Max.
V +0.3
DD
Units
Notes
1
V
IH1
V
V
V
V
V
IL1
0.8
1
V
OH1
—
1, 2
1, 3
V
OL1
0.4
I
µA
—
+50
4
JTAG
(V = V or V )
IN
SS
DD
1. All JTAG Inputs/Outputs are LVTTL Compatible only.
2. I
= -8mA at 2.4V.
OH1
OL1
3. I
= +8mA at 0.4V.
4. If JTAG is not used, signals TCK, TMS, and TDI may be left floating. These inputs are defaulted to V
.
DD
JTAG AC Test Conditions (TA = 0 to +70°C, VDD = 3.3V -5% + 10%)
Parameter
Symbol
Conditions
3.0
Units
V
Notes
V
Input Pulse High Level
Input Pulse Low Level
Input Rise Time
IH1
V
0.0
V
IL1
T
2.0
ns
ns
V
R1
T
Input Fall Time
2.0
F1
Input and Output Timing Reference Level
1. See AC Test Loading on page 11.
1.5
1
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
77H9965.T5
10/98
Page 14 of 22
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