IBM041811TLAB
IBM043611TLAB
32K x 36 & 64K x 18 SRAM
Preliminary
Timing Diagram (Read and Write Cycles)
tKLKH
tKHKH
tKHKL
K
tAVKH
A2
tKHAX
A3
A1
A2
SA
A4
tSVKH
SS
tKHSX
tKHWX
tKHWX
SW
tWVKH
tWVKH
tKHWX
tKHWX
SBW
tWVKH
tWVKH
G
tGHQZ
tKHQV
tKHQZ
tKHDX
Q2
D4
Q3
Q1
D2
DQ
tKHQV
tKHQX4
tDVKH
tDVKH
tKHDX
NOTES:
1. D2 is the input data written in memory location A2.
2. Q2 is output data read from the write buffer, as a result of address A2 being a match
from the last write cycle address.
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Use is further subject to the provisions at the end of this document.
77H9965.T5
10/98
Page 12 of 22
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