Discontinued (8/99 - last order; 12/99 - last ship)
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a
high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first
and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that
point the Write Command will have control of the DQ bus.
Minimum Read to Write Interval
(Burst Length = 4, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM high for CAS latency = 2 only.
Required to mask first bit of READ data.
DQM
NOP
READ A
WRITE A
DIN A0
NOP
DIN A1
DIN A1
NOP
DIN A2
DIN A2
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DIN A3
DIN A3
tCK2, DQs
CAS latency = 3
DIN A0
tCK3, DQs
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3264.E35855A
1/28/99
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