欢迎访问ic37.com |
会员登录 免费注册
发布采购

IBM0364804PT3B-360 参数 Datasheet PDF下载

IBM0364804PT3B-360图片预览
型号: IBM0364804PT3B-360
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 72 页 / 1201 K
品牌: IBM [ IBM ]
 浏览型号IBM0364804PT3B-360的Datasheet PDF文件第7页浏览型号IBM0364804PT3B-360的Datasheet PDF文件第8页浏览型号IBM0364804PT3B-360的Datasheet PDF文件第9页浏览型号IBM0364804PT3B-360的Datasheet PDF文件第10页浏览型号IBM0364804PT3B-360的Datasheet PDF文件第12页浏览型号IBM0364804PT3B-360的Datasheet PDF文件第13页浏览型号IBM0364804PT3B-360的Datasheet PDF文件第14页浏览型号IBM0364804PT3B-360的Datasheet PDF文件第15页  
Discontinued (8/99 - last order; 12/99 - last ship)  
IBM0364804 IBM0364164  
IBM0364404 IBM03644B4  
64Mb Synchronous DRAM - Die Revision B  
Bank Activate Command  
In relation to the operation of a fast page mode DRAM, the Bank Activate command corresponds to a falling  
RAS signal. The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the  
rising edge of the clock. The bank select address A12 - A13 is used to select the desired bank. The row  
address A0 - A11 is used to determine which row to activate in the selected bank. Activation of banks within  
both decks of a 2-high stacked device is allowed.  
The Bank Activate command must be applied before any Read or Write operation can be executed. The  
delay from when the Bank Activate command is applied to when the first read or write operation can begin  
must meet or exceed the RAS to CAS delay time (tRCD). Once a bank has been activated, it must be pre-  
charged before another Bank Activate command can be applied to the same bank. The minimum time inter-  
val between successive Bank Activate commands to the same bank is determined by the RAS cycle time of  
the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B  
and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is  
specified as tRAS(max)  
.
Bank Activate Command Cycle  
(CAS Latency = 3 tRCD = 3)  
T0  
T1  
T2  
T3  
Tn  
Tn+1  
Tn+2  
Tn+3  
CLK  
. . . . . . . . . .  
Bank A  
Col. Addr.  
Bank A  
Row Addr.  
Bank B  
Row Addr.  
Bank A  
Row Addr.  
. . . . . . . . . .  
ADDRESS  
RAS-CAS delay (t  
NOP  
)
RAS - RAS delay time (t  
)
RCD  
RRD  
Write A  
with Auto  
Precharge  
Bank B  
NOP  
Bank A  
Activate  
Bank A  
Activate  
. . . . . . . . . .  
NOP  
NOP  
COMMAND  
Activate  
: “H” or “L”  
RAS Cycle time (t  
)
RC  
Bank Select  
The Bank Select inputs, BS0 and BS1, determine the bank to be used during a Bank Activate, Precharge,  
Read, or Write operation.  
Bank Selection Bits  
BS0  
0
BS1  
0
Bank  
Bank 0  
Bank 1  
Bank 2  
Bank 3  
0
1
1
0
1
1
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
19L3264.E35855A  
1/28/99