Discontinued (8/99 - last order; 12/99 - last ship)
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is
registered. The DQs must be in the high impedance state at least one cycle before the interrupting read data
appears on the outputs to avoid data contention. When the Read Command is registered, any residual data
from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Read Command is
initiated will actually be written to the memory.
Minimum Write to Read Interval
(Burst Length = 4, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
WRITE A
DIN A0
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
don’t care
don’t care
DOUT B0
DOUT B1
DOUT B0
DOUT B2
DOUT B1
DOUT B3
DOUT B2
tCK2, DQs
CAS latency = 3
don’t care
DIN A0
DOUT B3
tCK3, DQs
Input data for the Write is masked.
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3264.E35855A
1/28/99
Page 17 of 72
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