Discontinued (8/99 - last order; 12/99 - last ship)
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from
memory locations (read cycle). Three parameters define how the burst mode will operate: burst sequence,
burst length, and operation mode. The burst sequence and burst length are programmable and are deter-
mined by address bits A0 - A3 during the Mode Register Set command. Operation mode is also programma-
ble and is set by address bits A7 - A13.
Burst sequence defines the order in which the burst data will be delivered or stored to the SDRAM. The two
types of burst sequence supported are sequential and interleaved. See the table below.
The burst length controls the number of bits that will be output after a Read Command, or the number of bits
to be input after a Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 or full
page (actual page length is dependent on organization: x4, x8, or x16). Full page burst operation is only pos-
sible using the sequential burst type.
Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation
implies that the device will perform burst operations on both read and write cycles until the desired burst
length is satisfied. Multiple burst with single write operation was added to support Write Through Cache oper-
ation. Here, the programmed burst length only applies to read cycles. All write cycles are single write opera-
tions when this mode is selected.
Burst Length and Sequence
Burst Length
Starting Address (A2 A1 A0)
Sequential Addressing (decimal)
0, 1
Interleave Addressing (decimal)
0, 1
x x 0
x x 1
x 0 0
x 0 1
x 1 0
x 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
n n n
2
1, 0
1, 0
0, 1, 2, 3
0, 1, 2, 3
1, 2, 3, 0
1, 0, 3, 2
4
2, 3, 0, 1
2, 3, 0, 1
3, 0, 1, 2
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
Cn, Cn+1, Cn+2, ......
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Not Supported
8
Full Page (Note)
Note: Page length is a function of I/O organization and column addressing.
x4 Organization (CA0-CA9); Page Length = 1024 bits
x8 Organization (CA0-CA8); Page Length = 512 bits
x16 Organization (CA0-CA7); Page Length = 256 bits
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3264.E35855A
1/28/99
Page 10 of 72
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