Discontinued (8/99 - last order; 12/99 - last ship)
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
Non-Minimum Write to Read Interval
(Burst Length = 4, CAS Latency = 2, 3)
T5 T6 T7 T8
T0
T1
T2
T3
T4
CLK
NOP
READ B
WRITE A
DIN A0
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DIN A1
DIN A1
don’t care
don’t care
DOUT B0
DOUT B1
DOUT B0
DOUT B2
DOUT B1
DOUT B3
DOUT B2
tCK2, DQs
CAS latency = 3
don’t care
DIN A0
DOUT B3
tCK3, DQs
Input data for the Write is masked.
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3264.E35855A
1/28/99
Page 18 of 72
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