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IBM0316809CT3-11 参数 Datasheet PDF下载

IBM0316809CT3-11图片预览
型号: IBM0316809CT3-11
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 2MX8, 10ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 100 页 / 1216 K
品牌: IBM [ IBM ]
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IBM0316409C IBM0316809C  
IBM0316169C  
16Mbit Synchronous DRAM  
Current State Truth Table (Continued) (Notes: 1)  
Command  
Current State  
Action  
Notes  
CS RAS CAS WE A11  
A10 - A0  
OP Code  
Description  
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
Mode Register Set  
ILLEGAL  
X
X
X
X
Auto or Self Refresh ILLEGAL  
L
H
H
L
Precharge  
ILLEGAL  
ILLEGAL  
ILLEGAL  
ILLEGAL  
4
L
H
L
BS Row Address Bank Activate  
4
Write  
Recovering  
with Auto  
Precharge  
H
H
H
H
X
L
Column  
Write  
4, 9  
4, 9  
BS  
BS  
X
L
H
L
Column  
Read  
No Operation; Precharge after tDPL  
No Operation; Precharge after tDPL  
No Operation; Precharge after tDPL  
ILLEGAL  
H
H
X
L
X
X
X
Burst Termination  
No Operation  
Device Deselect  
Mode Register Set  
H
X
L
X
X
OP Code  
L
L
H
L
X
X
X
X
Auto or Self Refresh ILLEGAL  
L
H
H
L
Precharge  
ILLEGAL  
L
H
L
BS Row Address Bank Activate  
ILLEGAL  
H
H
H
H
X
L
Column  
Write  
ILLEGAL  
BS  
BS  
X
Refreshing  
L
H
L
Column  
Read  
ILLEGAL  
No Operation; Idle after tRC  
No Operation; Idle after tRC  
No Operation; Idle after tRC  
ILLEGAL  
H
H
X
L
X
X
X
Burst Termination  
No Operation  
Device Deselect  
Mode Register Set  
H
X
L
X
X
OP Code  
L
L
H
L
X
X
X
X
Auto or Self Refresh ILLEGAL  
L
H
H
L
Precharge  
ILLEGAL  
L
H
L
BS Row Address Bank Activate  
ILLEGAL  
Mode Register  
Accessing  
H
H
H
H
X
Column  
Write  
ILLEGAL  
BS  
BS  
X
L
H
L
Column  
Read  
ILLEGAL  
H
H
X
X
X
X
Burst Termination  
No Operation  
Device Deselect  
ILLEGAL  
No Operation; Idle after two clock cycles  
No Operation; Idle after two clock cycles  
H
X
X
X
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Com-  
mand is being applied to.  
2. Both Banks must be idle otherwise it is an illegal action.  
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode  
is entered.  
4. The Current State refers only refers to one of the banks, if BS selects this bank then the action is illegal. If BS selects the bank not  
being referenced by the Current State then the action may be legal depending on the state of that bank.  
5. If CKE is inactive (low) than the Power Down mode is entered, otherwise there is a No Operation.  
6. The minimum and maximum Active time (tRAS) must be satisfied.  
7. The RAS to CAS Delay (tRCD) must occur before the command is given.  
8. Column address A10 is used to determine if the Auto Precharge function is activated.  
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.  
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.  
©IBM Corporation, 1996. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
07H3997  
SA14-4711-02  
Revised 05/96  
Page 29 of 100  
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