IBM0316809C IBM0316409C
IBM0316169C
16Mbit Synchronous DRAM
The above discussion does not apply when full page burst is programmed into the Mode Register. Full page
burst length works only with the sequential burst sequence and has no address boundaries. The SDRAM
device will continue bursting data even after the entire page burst length has been satisfied. The burst
sequence will start at the column address defined during the read or write cycle and will increment sequen-
tially until the highest order column address has been reached. At this point, the burst counter will reset to
address 0 and continue to perform burst read or burst write operations sequentially until either a Burst Stop
Command is issued, a Precharge Command is issued to the bursting bank, or until a new Read or Write
Command is issued which will interrupt the existing burst and begin a new burst at the new starting column
address.
Similar to Page Mode of conventional DRAM’s, a read or write cycle can not begin until the sense amplifiers
latch the selected row address information. The refresh period (tREF) is what limits the number of random col-
umn accesses to an activated bank. A new burst access can be done even before the previous burst ends.
The ability to interrupt a burst operation at every clock cycle is supported, this is referred to as the 1-N rule.
When the previous burst is interrupted by another Read or Write Command, the remaining addresses are
overridden by the new address once the CAS Latency has been satisfied.
Precharging an active bank after each read or write operation is not necessary providing the same row is to
be accessed again. To perform a read or write cycle to a different row within an activated bank, the bank must
be precharged and a new Bank Activate command must be issued. When both Bank A and Bank B are acti-
vated, interleaved (ping pong) bank Read or Write operations are possible. By using the programmed burst
length and alternating the access and precharge operations between the two banks, fast and seamless data
access operation among many different pages can be realized. When the two banks are activated, column to
column interleave operation can be done between two different pages. Finally, Read or Write Commands can
be issued to the same bank or between active banks on every clock cycle.
Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising
edge of the clock. The address inputs determine the starting column address for the burst, the Mode Register
sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page). The delay from the start
of the command to when the data from the first cell appears on the outputs is equal to the value of the CAS
latency that is set in the Mode Register.
Burst Read Operation (Burst Length = 4, CAS latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 1
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
0
1
2
3
t
CK1, DQ’s
CAS latency = 2
DOUT A
3
0
1
2
t
CK2, DQ’s
CAS latency = 3
DOUT A
DOUT A
DOUT A
DOUT A
3
0
1
2
t
CK3, DQ’s
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
07H3997
SA14-4711-02
Revised 05/96
Page 12 of 100
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