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IBM0118165T3-70 参数 Datasheet PDF下载

IBM0118165T3-70图片预览
型号: IBM0118165T3-70
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM, 1MX16, 70ns, CMOS, PDSO44, 0.400 X 0.825 INCH, TSOP2-50/44]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 31 页 / 350 K
品牌: IBM [ IBM ]
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IBM0118165 IBM0118165M  
IBM0118165B IBM0118165P  
1M x 16 10/10 EDO DRAM  
Refresh Cycle  
-50  
-60 / -6R  
-70  
Symbol  
Parameter  
Units  
Notes  
Min. Max. Min. Max. Min. Max.  
CAS Setup Time  
(CAS before RAS Refresh Cycle)  
tCSR  
tCHR  
tWRP  
5
5
5
ns  
ns  
ns  
CAS Hold Time  
(CAS before RAS Refresh Cycle)  
10  
10  
10  
10  
10  
10  
WE Setup Time  
(CAS before RAS Refresh Cycle)  
WE Hold Time  
(CAS before RAS Cycle)  
tWRH  
tRPC  
10  
5
10  
5
10  
5
ns  
ns  
RAS Precharge to CAS Hold Time  
Self Refresh Cycle - Low Power version only  
-50  
-60  
-70  
Symbol  
Parameter  
Units  
Notes  
Min.  
100  
Max.  
Min. Max. Min. Max.  
RAS Pulse Width  
tRASS  
tRPS  
tCHS  
tCHD  
µs  
ns  
ns  
µs  
100  
104  
-50  
100  
124  
-50  
1
During Self Refresh Cycle  
RAS Precharge Time  
During Self Refresh Cycle  
89  
-50  
350  
1
CAS Hold Time From RAS Rising  
During Self Refresh Cycle  
1, 2  
1, 2  
CAS Hold Time From RAS Falling  
During Self Refresh Cycle  
350  
350  
1. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation:  
If row addresses are being refreshed in an EVENLY DISTRIBUTED manner over the refresh interval using CBR refresh cycles,  
then only one CBR cycle must be performed immediately after exit from Self Refresh.  
If row addresses are being refreshed in any other manner (ROR- Distributed/Burst; or CBR-Burst) over the refresh interval, then a  
full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh.  
2. If tRASS > tCHD (min) then tCHD applies. If tRASS tCHD (min) then tCHS applies.  
Refresh  
-50  
Max.  
-60 / -6R  
Min. Max.  
-70  
Max.  
SYMBOL  
Parameter  
Units  
ms  
Notes  
1
Min.  
Min.  
SP version  
LP version  
16  
16  
16  
tREF  
Refresh Period  
128  
128  
128  
1. 1024 cycles.  
©IBM Corporation, 1995. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
28H4721  
SA14-4223-01  
Revised 12/95  
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