IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
Write Cycle (Early Write)
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
VIH
UCAS
tCAS
LCAS
VIL
tRAD
tASR
tASC
tRAH
tCAH
VIH
VIL
Address
Row
Column
tWRH
tWRP
tWCS
tWCH
VIH
VIL
tWP
WE
OE
NOTE 1
VIH
VIL
tDS
tDH
VIH
VIL
DIN
Valid Data In
VOH
VOL
DOUT
Hi-Z
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 13 of 32
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