IBM0118165M IBM0118165
IBM0118165P IBM0118165B
1M x 16 10/10 EDO DRAM
Read Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRCD
tRSH
tCRP
VIH
UCAS
LCAS
tCAS
VIL
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH
Address
Row
Column
VIL
tRCH
tRRH
tWRP
tWRH
tRCS
VIH
VIL
NOTE 1
WE
OE
tAA
tOES
VIH
VIL
tOEA
tDZC
tCDD
tDZO
tOED
VIH
VIL
DIN
Hi-Z
tCAC
tCLZ
tOFF
tOEZ
VOH
VOL
DOUT
Hi-Z
Valid Data Out
Hi-Z
tRAC
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H”: or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 12 of 32
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