HY29F002T
AC CHARACTERISTICS
Read Operations
Parameter
Speed Option
- 45 - 55 - 70 - 90
Description
Test Setup
Unit
JEDEC
Std
tAVAV
tRC Read Cycle Time (Note 1)
Min 45
55
70
90
ns
ns
CE# = VIL
OE# = VIL
tAVQV
tACC Address to Output Delay
Max 45
55
70
90
tELQV
tEHQZ
tGLQV
tGHQZ
tCE Chip Enable to Output Delay
OE# = VIL Max 45
Max 15
55
15
25
15
70
20
30
20
90
20
35
20
ns
ns
ns
ns
ns
tDF Chip Enable to Output High Z (Note 1)
tOE Output Enable to Output Delay
tDF Output Enable to Output High Z (Note 1)
CE# = VIL Max 25
Max 15
Read
Min
0
Output Enable
Hold Time (Note 1)
tOEH
Toggle and
Data# Polling
Min
Min
10
ns
ns
Output Hold Time from Addresses, CE#
or OE#, Whichever Occurs First (Note 1)
tAXQX
tOH
0
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 7 for test conditions.
tRC
Addresses
CE#
Addresses Stable
tACC
tOE
OE#
tOEH
tDF
WE#
Outputs
RESET#
tCE
tOH
Output Valid
Figure 13. Read Operation Timings
Rev. 4.1/May 01
23
HYNIX [ HYNIX SEMICONDUCTOR ]
