GMS81C2020/GMS81C2120
Hyundai Micro Electronics
19.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to "0" by a reset or an in-
struction. Interrupt acceptance sequence requires 8 fOSC (2
µs at fXI=4MHz) after the completion of the current in-
struction execution. The interrupt service task is terminat-
ed upon execution of an interrupt return instruction
[RETI].
2. Interrupt request flag for the interrupt source accepted is
cleared to "0".
3. The contents of the program counter (return address)
and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.
4. The entry address of the interrupt service program is
read from the vector table address and the entry address
is loaded to the program counter.
Interrupt acceptance
1. The interrupt master enable flag (I-flag) is cleared to "0"
to temporarily disable the acceptance of any following
maskable interrupts. When a non-maskable interrupt is
accepted, the acceptance of any following interrupts is
temporarily disabled.
5. The instruction stored at the entry address of the inter-
rupt service program is executed.
System clock
Instruction Fetch
SP-2
PSW
V.L.
V.H.
New PC
OP code
SP
SP-1
PC
Address Bus
Data Bus
Not used
PCH
PCL
V.L.
ADL
ADH
Internal Read
Internal Write
Interrupt Processing Step
Interrupt Service Task
V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.
Figure 19-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
When nested interrupt service is required, the I-flag should
Basic Interval Timer
Vector Table Address
be set to "1" by “EI” instruction in the interrupt service
program. In this case, acceptable interrupt sources are se-
lectively enabled by the individual interrupt enable flags.
Entry Address
012
0FFE6
0FFE7
H
H
H
0E
2E
0E312
0E313
H
H
0E3
H
H
Saving/Restoring General-purpose Register
H
During interrupt acceptance processing, the program
counter and the program status word are automatically
saved on the stack, but accumulator and other registers are
not saved itself. These registers are saved by the software
if necessary. Also, when multiple interrupt services are
nested, it is necessary to avoid using the same data memory
area for saving registers.
Correspondence between vector table address for BIT interrupt
and the entry address of the interrupt service program.
A interrupt request is not accepted until the I-flag is set to
"1" even if a requested interrupt has higher priority than
that of the current interrupt being serviced.
68
preliminary
Nov. 1999 Ver 0.0
HYNIX [ HYNIX SEMICONDUCTOR ]
